The prior art recognizes semiconductor memory cells that utilize field effect transistors formed on a substrate so as to control current flow through a channel region between source and drain regions. A control gate overlays a floating gate which overlays the channel region. To read the cell, the control gate is typically charged (positive in the case of an N channel device) to draw electrons into the channel and permit current flow. However, this effect may be blocked by the floating gate positioned between the channel and the control gate. The floating gate influences the current flow in the channel as a function of the charge trapped on the floating gate. The memory cell is programmed by tunnelling charge carriers on or off the floating gate with suitably applied electric fields that act across carefully dimensioned thin oxide layers, the size and thickness of which are critically important to proper operation.
Numerous design objectives need to be met with these memory cells. These different objectives are often inherently conflicting. For example, the floating gate acts on the channel with electric fields and thus must be capacitively coupled to the channel. It is important that this capacitance be well known and predictable in order to have reliable and consistent operation. However, the prior art thin oxide layers, where tunnelling takes place, are notoriously unpredictable in this respect, because they are so thin, typically less than 200 angstroms. Their thinness enhances their share of the total capacitance while at the same time, making the magnitude of that share unpredictable. In addition, the thin oxide tunnel regions, being so thin, are physically fragile and defects are easily introduced by any environmental stress they encounter during manufacture.
A typical prior art cell is exemplified by U.S. Pat. No. 4,162,504. This patent teaches the use of a narrower floating gate which does not extend completely across the channel region and thus avoids alignment with the edges of the source and drain regions. The gate is thereby isolated from possible avalanche breakdown at the junction. This solution is not satisfactory, however, because of insufficient capacitive coupling between the floating and control gates in practical cell sizes. Also the thin oxide is coextensive with the floating gate which is objectionable as will be discussed hereinafter.
Another prior art approach is taught in U.S. Pat. No. 4,203,158 which proposes to reduce the thin oxide tunnelling area to a small fraction of device area (column 1, line 66) by moving it to a "third region". Several different embodiments are suggested with several different locations for this third region, all of which suffer from some problems. For example, in FIG. 1, the third region 14a is located at a PN junction and thus could be subjected to the avalanche breakdown problem discussed in U.S. Pat. No. 4,162,504. In FIG. 2, another third region location 36 is contemplated, again at a PN junction possibly subject to avalanche breakdown. Also, this layout would create a larger cell. As disclosed, the cell is incapable of being erased without adding a fourth electrical connection to region 36 which would make the cell very large indeed. Still another third region location is taught in FIGS. 3 and 4, again at the objectionable location near both junctions and also along the sides of the active channel next to the field oxide (column 6, lines 5-21) which location is also objectionable as will be explained in detail later. Finally, U.S. Pat. No. 4,203,158 describes the preferred, and perhaps the worst, location for the third region in FIG. 5, namely, displaced off to the side at region 60. Region 60, being off to one side, causes the whole memory cell to be much larger, thus reducing the density of components on the chip and necessitating larger chips. Also troublesome is the fact the edges of the thin oxide layer are determined by the edges of the field oxide (column 7, line 63-67) which creates many problems. Firstly, the edge of the field oxide layer is an area of high mechanical stress that can degrade the fragile thin oxide layer and introduce uncertainties in performance. Secondly, there are often trace amounts of silicon nitride left over at the edge of the field oxide from previous operations which degrades the quality of the thin oxide at this point. Thirdly, the actual location of the field oxide edge is less controllable and results in additional uncertainties in the size of the thin oxide area.
Still further problems are created when U.S. Pat. No. 4,203,158 etches the two layers of polysilicon for the gate line 52 in FIG. 12. This etching step inevitably attacks the edges of the delicate and fragile thin oxide layer. The problem is so serious, that it is even mentioned in column 9 of U.S. Pat. No. 4,203,158 where a "blanket" is proposed to protect the thin oxide during subsequent manufacturing steps. The present invention avoids all of the above problems with the novel layout described hereinafter.